1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof.
2. Background of the Related Art
Information storage in NOR type flash memory cells is a mode in which difference in cell current due to difference between the threshold voltage (Vt) when charges (electrons) are stored at the floating gate and the threshold voltage (Vt) when charges (electrons) are not stored at the floating gate is compared and the status of the flash memory cell is then read.
Referring now to FIG. 1, a data storage method in a general flash memory cell will be described.
As shown in FIG. 1, current that is outputted when a constant voltage is always applied to the control gate and current that is always constantly outputted from the reference cell are compared in the sense amplifier. A case where lots of current flows and a case where a small amount of current flows are set to “0” and “1”, respectively, which is called 1 bit.
However, a method of storing 1 bit at 1 (one) cell needs the same number of the cell to the degree of integration as the degree of integration in the flash memory cell is increased. In other words, a 64M flash needs cells of 226 in number. Therefore, the multi-level cell (MLC) was developed in order to address this problem. Further, a method of fractionating the threshold voltages (Vt) of the flash memory cell regardless of the flash cell structure and then displaying their states has been developed. This method may be developed for the NAND type flash memory device as well as the NOR type flash memory device.
Most of the multi-level cells store information by fractionating the threshold voltage (Vt) into four states, as shown in FIG. 2. The states could be classified into “11”, “10”, “01” and “00”, respectively. In other words, the multi-level cell has a structure in which 2-bit (four states) can be stored at 1 (one) cell. It would be the most ideal one if the threshold voltage (Vt) states are infinitely divided. So far, however, it is common to divide the threshold voltage (Vt) into four states.
However, in a common 2-bit multi-level cell, four states are divided into one stack cell. This method may have a problem when charge loss occurs due to charge retention. In other words, when an erased state is changed to a programmed state, charges of about 3000 in number are gathered in the floating gate. If there occurs charge loss when 3000 charges in number are divided by 4 states, it is recognized as another state. Thus there is a high probability that fail may happen.